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AGC

DeadTime

DeadZone

Delay

Diff

FreqDet

Gain

Integ_r

Laplace

LeadLag

Lim

LimExt

MUX

PhaseDet

PID, PIDd

PLL

RMS

SampledSource

SlewRate

SOGI

UpDnSpl

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StateSpace

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Subcircuits in filt.sub:

AGC

Automatic gain control, outputs the input as unity amplitude, and the gain. The input is IN (floating), and the outputs are OUT, for signal, and G, for the gain (1Ω, both). F is the external frequency control, anything connected to this pin overrides internal settings for f. Due to the nature of the filtering, varying envelope signals may not get a "stiff" 1V amplitude, but it may vary. Here's an example of external frequency control. The source is a sweep generated by A1, frequency-modulated by B1, and amplitude-modulated by I1+R1. The sweep is logarithmic and G1+V1 restore the frequency to its usable values for the AGC. Since the amplitude is variable, most of the time, and since the filter cannot respond instantly, the amplitude is not exactly unity. The effect is more pronounced in the interval 50ms..60ms, and 60ms..70ms, where the slope is more rapidly changing. f Hz Working frequency, default 1k min V Minimum estimated gain, to avoid division by zero, default 0.1 filt=<1,2> - Selects between two adaptive filtering methods: 1 ⇒ moving average (very low group delay, but noisy) 2 ⇒ 4th order Bessel (more delay, but better filtering, default) k=(0..1] - Multiplier for the Bessel corner frequency fc, k=1 means fc=f, default 0.2 lim V Internal limits to avoid clipping, default 1g

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DeadTime

Dead-time. The input is floating and the output is 1Ω resistance. Vhigh,Vlow V Output logic levels, defaults <1,0> dt s Delay, default 1u ref V Input logic threshold, default 0.5 td,tripdt s LTspice's specific for A-devices, defaults <0,0>

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DeadZone

Dead-zone. The input is floating and the output is 1Ω. The upper/lower clipping limits should not have too large values, as these are used in a linear interpolation. Precision may be affected when, say lim=1T and dz is in the mV range, or lower. dz=<0..∞> V Anything between <-dz..dz> is zero, default 1 lim V Upper/lower clipping limits, default 1k Cout F Output capacitance for aid in convergence, default 0

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Delay

Delay. It works as either z-1 or e-st. The input is floating and the output is 1Ω resistance. t s The time delay, its signum controls the output's, default 1m

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Diff

Differentiator. The input is floating and the output is {1/ωc}Ω. tau s The time-constant, default 1m Rser, Rpar Ω LTspice's specific for inductor, defaults <0,0>

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FreqDet

Frequency detector. The inputs are floating and the output is 1Ω. It works with biased and modulated signals, too, as long as the modulation doesn't interfere with the input differentiator. limit s The lowest estimate for the period, default 1m gain=<-∞..∞> - Sets the gain for the input differentiator, for the cases when the input signal is too weak/strong, default 1 tripdt s LTspice's specific for A-devices, default 1u lim V Internal limits to avoid clipping, default 1g

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Gain

Gain/buffer. G=<-∞..∞> - Gain, default -1 dB=<0,1> - 0 ⇒ linear gain (default) 1 ⇒ dB gain Rout Ω Output resistance, default 1 Cout F Output capacitance for aid in convergence, default 0

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Integ_r

Integrator with reset and external period control. The input is floating and the output is 1Ω. External reset is at RESET (the vertical pin in the middle, subcircuit name 1), 1GΩ internal pulldown. There are two different behaviours for reset, controlled by the parameter edge: reset and hold, and edge-triggered reset. The difference is illustrated in this example: V(a) (black) resumes integration instantly, after each rising edge of the reset, while V(b) (blue) holds the reset for as long as V(reset) (red) is high. External control for the period is at pin TAU (in the corner), anything connected to it overrides internal settings for tau (but not its signum), Rin=1GΩ. sgn(tau) == sgn(V(out)). tau s The period of integration, its signum controls the output's, default 1m edge=<0,1> - Selects the behaviour of the reset: 0 ⇒ resets and holds the reset for as long as V(RESET)>ref (default) 1 ⇒ edge-triggered reset, mod()-like behaviour ref V Logic threshold for external reset, default 0.5 lim V Internal limits to avoid clipping, default 1g fmax Hz Estimated maximum bandwidth for the signal, default 1Meg

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Laplace

2nd order Laplace transfer function. The input is floating and the output is 1Ω. It's limited to 10dB/dec or 20dB/dec. The transfer function must not be less than strictly proper. f Hz Frequency scaling, relative to b0/b2, default 1 g - Gain, linear, default -1 a2, a1, a0 - Numerator terms, indices represent powers of s, defaults <1,2,10> b2, b1, b0 - Denominator terms, indices represent powers of s, b2 must not be null, defaults <2,3,1> Rpar Ω LTspice's specific for capacitors, default 1g

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LeadLag

Voltage controlled lead/lag. The input is floating and the output is 1Ω. Pin CTL allows for external phase control, anything connected to it overrides internal settings for tau, Rin=1GΩ. If the external control also has Rin=1GΩ, the control is transformed from a*x to a*x + b. Combinations with different I/O resistances and voltages are also possible. Example of phase detection with LeadLag and PhaseDet. f Hz The frequency of the input signal, default 1k phi=<-∞..∞> rad Phase displacement control, it can take any value, but it's wrapped internally between <-π..π>, default π/4 lim V Internal limits to avoid clipping, default 1g

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Lim

Hard- or soft-limiter. The input is floating and the output is 1Ω. The soft-limiting is an asymmetrical tanh(), so be careful when using like-wise inputs. Min, Max V The lower and upper limits, defaults <-1,1> soft=<0,1> - Selects the type of limiting: 0 ⇒ hard limit (default) 1 ⇒ soft limit Cout F Parallel capacitance for aid in convergence, default 0

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LimExt

Hard-limiter with external limits. The input is floating and the output is 1Ω. The external limit inputs are 1GΩ, anything connected to these pins override internal settings. Min, Max V The lower and upper limits, defaults <-1,1> lim V Internal limits to avoid clipping, default 1g. Cout F Parallel capacitance for aid in convergence, default 0 tau s LTspice's specific for A-devices, should not be zero, default 1n.

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MUX

8-channel multiplexer. It works like this: If int(V(CTL))==x then V(out)==V(x) If int(V(CTL))<1 or int(V(CTL))>8 then V(out)=0 The inputs and the external control pin, CTL are floating, and the output is 1Ω. Cout F Output capacitance for aid in convergence, default 0

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PhaseDet

Phase detector, relative to a fixed, zero displacement fundamental, starting at t=0. The input is floating and the output is 1Ω. f Hz The working frequency, default 1k deg=<0,1> - Selects the units for the angle: 0 ⇒ rad 1 ⇒ deg (default) Rpar Ω LTspice's specific for capacitors, default 1g

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PID

Proportional-Integral-Derivative control. Any combination works: PID, PI, PD, ID, P, I, D, none. The input is floating and the output is 1Ω. PID is the analog version, PIDd is the digital version. There is no internal s&h, so you'll have to either supply your own, or rely on the behaviour of the tlines. Kp - The proportional gain, default 0 Ki - The integral gain, default 0 Kd - The derivative gain, default 0 min, max V The minimum and the maximum limits for the anti-windup, defaults <0, 0> (anti-windup disabled) Klim - The anti-windup gain, default 1 ic V Initial conditions, default 0  PIDd only: Ts s The sampling period, default 1m method - Selects the method of integration: 0 ⇒ forward Euler (default) 1 ⇒ backward Euler 2 ⇒ trapezoidal Rpari, Rserd Ω Shunt and series resistances for the integrator and the differentiator, defaults <1g, 1m>

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PLL

Phase locked loop. The input is floating, the SIN and COS pins output unity amplitude sin()/cos() (Rout=1Ω), THETA outputs the angle as mod(x,2π) (Rout=1Ω), and the FREQ pin outputs the frequency (Rout={ Kp - jKi }Ω). It was thought as a grid-tied utility, but it works with higher frequencies, as well: example. V1 generates the unity amplitude, base frequency signal, G1 amplifies it tenfold, V2 adds an extra 5th harmonic, while the PLL's SIN output is compared to the unity input. The transients for this difference and the detected frequency are displayed. Note the scaling of the loop filter's parameters compared to their defaults: the frequency is 1000x higher, so Kp=6.1*103, Ki=81*106. f Hz The central frequency, default 50 Kp, Ki - The parameters for the PI loop filter, defaults <6.1,81> Kerr - Quality factor for the input SOGI, default 2 ic V Initial guess for the loop filter, default f lim V Internal limits to avoid clipping, default 1g

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RMS

Root mean square detector. It's a behavioural approach on Linear Tech's LTC1966↗. The input is floating and the output is {-j/ωc}Ω. fc Hz Corner frequency for the 2nd order filter, default 100 b1, b0 - Denominator terms for the lowpass prototype filter, indices reflect powers of s, defaults <3,3> (Bessel) lim V Internal limits to avoid clipping, default 1g

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SampledSource

LTspice's SINE and PULSE sources, sampled. Only one of them can be active at a time. The parameters are the same as LTspice's, with some exceptions and additions. The positive and negative output pins are marked with + (internal name: 1) and - (internal name: 2), respectively. The clock appears at pin CLK and is referenced at the negative pin; useful for providing, or receiving external sync. Rout=1GΩ. The original, non-sampled waveform is on pin CTS (internal name 3). Rout=0. f0 Hz The sampling frequency. If external sampling is needed, it needs to be referenced at pin 2; setting f0=0 will avoid unnecessary slow-downs by disabling the internal clock. Default 1k SP=<0,1> - Selects the type of source: 0 ⇒ SINE (default) 1 ⇒ PULSE td s Delay time of the clock pulse (rising edge), default 0 tr s Rising edge of the clock pulse, default 1m/f0 Rout=<0..∞> Ω Rout>0 ⇒ voltage source (default 1Ω) Rout=0 ⇒ current source Voffset, Vamp, Freq, Tdelay, Theta, Phi, Ncycles - The parameters for the SINE source, Tdelay replaces Td. Defaults: Voffset=0 Vamp=1 Freq=100 Tdelay=0 Theta=0 Phi=0 Ncycles=0 V1, V2, Tdelay, Trise, Tfall, Ton, 1/Freq, Ncycles - The parameters for the PULSE source, 1/Freq replaces Period. Defaults: V1=0 V2=1 Tdelay=0 Trise=10m Tfall=0 Ton=0 1/Freq=10m Ncycles=0 ac, acphase V, deg The AC amplitude and phase, common to both types of sources, defaults <1,0> vhigh, vlow V LTspice specific for A-devices, defaults <1k,-1k> tripdt s LTspice specific for A-devices, default 0

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SlewRate

Slew rate limiter. The input is floating and the output is {1-1/(s*Cout)}Ω (ever so slightly capacitive). Rise, Fall V/s Rising and falling slopes, respectively, default <4.5,-4.5> t0 s Period for internal delay. Lower values improve accuracy, at the cost of increased simulation time. A good compromise is in the range of 0.1%..1% of the input signal's frequency. Default 1m Cout F Output capacitance for aid in convergence, default t0/1k

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SOGI

Second order generalized intergator, with external frequency control. The input is floating, the quadrature outputs are {-j/(2π)}Ω, and the frequency control pin, F, has a 1GΩ internal pulldown. Anything connected to the frequency pin overrides internal f settings. f=<0..∞> Hz Frequency, default 50 ke - Quality factor set by the error amplifier, default 2 lim V Internal limits to avoid clipping, default 1g

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UpDnSpl

Up-/down-sampler, with or without external sync. The input is marked with a squared arrow and is floating, and the output is 1Ω. The pins on the bottom are the I/O clock, marked with an input, triangular arrow (floating), and the output sync clock, marked with an outgoing arrow (Rout=0). Example with SampledSource and UpDnSpl. The upsampler is using the internal clock (f0>0, f0==finput), and the downsampler uses external synchronization (f0<0, |f0|==finput). The value of index dictates the beginning of the sample relative to the input. f0 Hz The sampling frequency. f0<0 ⇒ external syncronization (must match input's clock) f0>0 ⇒ internal clock (default, 1k) f0=0 ⇒ bypass N=<-∞:∞> - Sets the upsampler's or downsampler's rate: N≥2 ⇒ upsampler (default, 2) N≤2 ⇒ downsampler Anything else means bypass index=<0:|N|-1> - Sample offset, default 0. For example, if the input is [0,1,2,3,...]: N=-4, index=2 ⇒ [2,6,10,14,...] N=-4, index=1 ⇒ [1,5,9,11,...] N=4, index=2 ⇒ [0,0,o,0; 0,0,1,0; 0,0,2,0; 0,0,3,0; ...] ref V Logic threshold for the downsampler's clock, default 0.5 lim V Internal limits to avoid clipping (downsampler), default 1k tripdt s LTspice's specific for A-devices, default 1u of the resulting upsampler's (f0*N) or downsampler's (f0/N) clock

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Subcircuits in statespace.sub:

StateSpace

1st, 2nd, and 3rd order SISO state-space block. The input (marked with a squared arrow) is floating and the output is 1Ω. The parameters use two indices that mark the matrix elements. All the parameters default to zero to make their modification easier after placing the symbol in the schematic. This way, when a first order block is needed, there's no need to go through the trouble of nullifying or setting all the other terms. Depending on the case, not all parameters are needed. The table below shows which parameters can be used, and which are safe to ignore, marked with 0. A B C D ic 1st A11 0 0 0 0 0 0 0 0 B11 0 0 C11 0 0 D11 ic1 0 0 2nd A11 A12 0 A21 A22 0 0 0 0 B11 B21 0 C11 C12 0 D11 ic1 ic2 0 3rd A11 A12 A13 A21 A22 A23 A31 A32 A33 B11 B21 B31 C11 C12 C13 D11 ic1 ic2 ic3 Here's an example with a 2nd order, to show parameter usage. A11 A12 A13, A21 A22 A23, A31 A32 A33 - The A matrix B11,B21,B31 - The B vector C11,C12,C13 - The C vector D11 - The D parameter ic1,ic2,ic3 - The three initial conditions

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