LTspice goodies - Digital models

A few notes:

All the devices are idealized and their use should be fairly straight-forward.
Some of the models have different names in the .subckt definition, compared to what is displayed by the symbol, so the description will follow the visual cues in the symbol, not the hard-coded notation.
The MSB is Q[0] and the width of the output bus is relative to it. For example, if N=12, the active outputs are Q[0:11], and Q[12:15] are inactive (floating).
The inputs are floating and the outputs have 1Ω resistance, except where otherwise noted.
Because of the above, grounding is necessary if inputs are not used, but only if N>{number_of_inputs}.
Where the inputs/outputs are marked as a bus, the net must be named as a bus, too, otherwise all the connections will be shortcircuited.

Here's an example for the last two points:
Bus-naming and grounding unconnected inputs

Bus-naming and grounding unconnected inputs

Quick menu:
0101.sub:: ADC16; CNT16asy; DAC16; JKflop; Quant16
Examples
Downloads

Subcircuits in 0101.sub:

ADC16

16bit analog to digital converter.

Q[0:15] (subcircuit names: [100:115]) is an N bit bus output.


N=<1..16>	-	Number of bits for the conversion, default 16
Vhigh,Vlow	V	Output logic levels, high and low, respectively, defaults <1,0>
VinH,VinL	V	Input signal range, not necessarily bipolar, defaults <32767,-32768>

td,tripdt	s	LTspice's specific for A-devices, defaults <0,0>

ADC16

CNT16asy

16bit asynchronous counter.

Q[0:15], _Q[0:15] (subcircuit names: [100:115], [200:215]) are complementary logic bus pins.
S, R (subcircuit names: 666, 999) are set and reset pins, respectively, with internal 1GΩ pulldowns.
The subcircuit name for the CLK pin is -1.


N=<1:16>	-	Number of bits for counting, default 16
Vhigh,Vlow	V	Output logic levels, default <1,0>

td,tau	s	LTspice's specific for A-devices (td should not be set null!), defaults <10n,0>
ic	V	Initial state for the true output, default 0

CNT16asy

DAC16

16bit digital to analog converter.

D[0:15] (subcircuit names: [100:115]) is a bus pin.
The output's resistance is {1/sum(2^-k,k,0,N-1)}Ω.


N=<1:16>	-	Number of bits for the conversion, default 16
Vhigh,Vlow	V	Output levels, not necessarily bipolar, defaults <32767,-32768>
ref	V	Logic input threshold, default 0.5

td, tripdt	s	LTspice's specific for A-devices, defaults <0,0>

DAC15

JKflop

J-K flip-flop.

J, K, CLK are floating inputs.
PRE, CLR are the set and rese pins, respectively, with 1GΩ internal pulldown.
The ground pin is RTN and cannot be left floating!


Vhigh,Vlow	V	Output logic levels, defaults <1,0>

td	s	LTspice's specific for A-devices (should not be set null!), default 10n

JKflop

Quant16

16bit quantizer.


N=<1:16>	-	Number of bits for the conversion, default 16
VinH,VinL	V	Input signal range, not necessarily bipolar, defaults <32767,-32768>
type=<1:4>	-	The type of rounding: 1 ⇒ int() (default) 2 ⇒ ceil() 3 ⇒ floor() 4 ⇒ round()

tripdt	s	LTspice's specific for A-devices, default 0.

Here are a few examples of usage (links to images opening up in a new window/tab):

Chain-connecting ADC16 with DAC16 is equivalent to using Quant16 with type=3 (floor() conversion).
The bus naming between the ADC16 and DAC16 has been limited to a 12 bit line, since N=12, both outputs have identical values for same time point, and the hidden parameter, tripdt, has been used to enhance the dynamic range.
J-K filp-flop
For easyness in comparison with the Wikipedia's example↗. Note that the ground pin is not left floating.
CNT16 and DAC16 interconnection.
Connecting CNT16asy with DAC16 is just as easy. The spikes are due to the fairly large timestep compared to the temporal dynamic range, but also due to the misalignments of the pulses (and their rise/fall/tau/etc).

The README file lists all the files inside the respective archive:

0101.zip (7374B): MD5=b836b9cfb82a5f888aea091f2786e1e7; SHA256=c4bde3aac8a92a44181abfaa515816cafc3e0bba5d81313aa90a41297f1f0e80