Note: Do not save the schematics after usage because they may be used in later examples.
Note: Opening the schematics from the links is best done with a Click+Drag over an existing opened instance of LTspice.

The same two methods apply here, as well.
In .TRAN there are several options, displayed in a rather ascending order (simulation-wise):
  1. Use continuous-time signal at the input. This has two possibilities of its own:
    1. Use SH=0 ⇒ the fastest response, continuous-time output, but unreal. If the input has smooth timesteps (e.g. a sine), the output will be the same (this may be useful with the Hilbert transfomer, for example).
    2. Use SH=1 ⇒ slower, sampled output, but makes I/O comparison difficult.
  2. Use sampled input, closer to reality, more choices:
    1. Don't use a clock, internal (SH=0) or external ⇒ there may be spurious spikes, particularly at low levels, though sampled output; more precisely, the input must be properly sampled.
    2. Don't use internal clock (f0<0) while the external clock (SH=1) is a sine source with SINE(0.5 0.5 {f0} 0 0 {-delay}) ⇒ smoother timestep but also very prone to spikes and sampling errors;
    3. Use external sync (i.e. the input's, implies SH=1) ⇒ there's always the risk of sampling on the rising edge1, but which can be avoided by setting the signal's S&H ref<0.5 (and/or ref>0.5 for Filter), or by imposing a value for td (in my experience, td=0.25/f0 seems to work best) ⇒ this is preferred because of the speed gain, i.e. only one clock source instead of more;
    4. Use internal clock (implies SH=1) ⇒ same hidden parameters tinkering as in the above c) point need to be set to avoid sync problems. This has the most stable output, but is also the slowest.
1due to LTspice being a dedicated analog simulator, the transitions are treated as regular transients and tend to get distorted in time.

To help speeding things up a bit for the latest option, a small trick can be employed: since for the sampling process only the rising edge is needed, the pulse source can be set with only Trise and Tperiod, resulting in a default 10% falling edge and one less point (Ton) to be calculated ⇒ same result, faster time.
As a "golden rule", in .ACSH=0 and in .TRANSH=1, but there can be exceptions to the rule.
The following table lists some of the key parameters which, when set to zero, allow various optimizations possible. There can only be one null parameter at a time.
Any of the following examples can be used to verify the table.
A normalized unity gain Chebyshev_IIR LP is chosen, with 1024Hz sampling frequency, -3dB@128Hz, 1dB ripple and -60dB@160Hz for an .AC analysis.
  1. Order automatically determined:
  2. SH=0 is to disable LTspice's S&H A-device, it doesn't allow .AC passing through and Fact=1 is for normal filter behaviour, interpolation/decimation is not needed now.

  3. Keeping the previous settings but with specified order:
  4. For a time domain impulse response, the two cards need to be switched. Since the input is already a well-shaped impulse, SH may be left null.
A comparison to the Analog active example. The sampling frequency is chosen ten times greater than ωc.
  1. N=0:

  2. N>0:
  3. Optional, the Analog active Butterworth with the same settings can be placed besides for comparison.
An InvChebyshev_IIR with 6dB gain, 48kHz sampling frequency, 2.5kHz center frequency, -1dB@3.75kHz pass-band and -100dB@5.25kHz stop-band.
  1. Minimum order to meet the requirements:

  2. The previously found out order, specified:
  3. The .TRAN simulation shows its response for a one octave sweep of a sampled sine input. To avoid being the slowest (2-d), option 2-b is used.
    There may be some sampling errors if the filter is a Cauer_IIR, but they will only be visible for values so small that they shouldn't matter.
For simplicity, the same example from the previous point is used and transformed into a Cauer_IIR BS by renaming InvChebyshev_IIRCauer_IIR and by switching the values of BWpBWs between themselves. The result can be used to also compare the .TRAN sweeps.
As warned, the simulation may take a second or two to start.
A rate of 4 and a familiar sampling frequency of 44.1kHz is used for a -3dB@20kHz (the FIR variant will use similar settings) and 120dB attenuation.
The simulation card has as Stop Frequency {22049*4}, 4 representing the rate and 22049 - the π frequency for unity rate (normal filter), minus 1Hz; the reason: LTspice, given enough data points, will show the attenuation @π as a very low value, possibly a few kdB, which is as it should be, but it almost obscures the response of interest, most of it residing within <10dB..-110dB>. This example is not one of the cases, though, as the order is even.
Decimation can also be tried with negative numbers (i.e. Fact=-4).
Visualizing the effect of interpolation can be done by changing the simulation cards and setting SH=1, where the limit of the audio domain, a 20kHz signal, is sampled at 44.1kHz and then interpolated at the above rate of 4. The gain is set to 4⋅1.4142 to allow a better matching for I/O amplitudes.
Setting test=1 will enable voltages at nodes BilTran and freqs. To avoid waiting the whole 100ms, the .TRAN can be changed to a lower value, say 9mssim=9m.
Pin 0.2 outputs a voltage in four steps. Following the explanation, V(freqs) has four values: the first quarter of the simulation is the value of the lower pass-band frequency, 1.25kV (VHz), then the 2nd time step has the value of the lower stop-band frequency, 1kV, the 3rd is the upper pass-band frequency, 5kV and the next is the upper stop-band, 6.25kV.
V(BilTran) goes in the same manner. The time span is first divided in six (9ms/6 = 1.5ms), one for each term of the bilinear transform, in this order: A2[n], A1[n], A0[n], B2[n], B1[n] and B0[n]. Each of these parts is again divided into N parts: 1.5ms/15 = 0.1ms (N=15, this is why .TRAN 9m has been chosen). Each 0.1ms represents one value of the coefficients. For example B0[1:15] (the last time segment, <7.5ms..9ms>) starts at 7.5ms until 7.6ms with B0[0], then until 7.7ms it's B0[1] and so on, until the last coefficient, <8.9ms..9ms>, B0[15].
If fc=0, the filter is now a LP and, with test=1, the second half of the time scale for V(freqs) is zero; for V(BilTran), each 6th part is divided in two and only the first half outputs the values.
The simulation lasts longer now and it does so for Butterworth_IIR and Chebyshev_IIR, too, but the "heavy-wait" is with Cauer_IIR: it will look as if the window is frozen, patience is really the answer here. Unwrapping all those functions for a behavioural voltage as a function of time does not come cheap.

©Vlad, 2008 - 2015