Name 
Description 
Symbol 
Parameters 

AGC 
Automatic gain control, provides the gain for unity peak amplitude and the input signal with unity gain. Due to the nature of the implementation, the output has one period delay and may not give unity output for greatly varying signals at the input; this is most visible for external, variable control. 
IN 
Input, floating 
F 
External frequency control, floating (may be left floating if not used) 
OUT 
Signal output, 1 Ω 
GAIN 
Gain output, 1 Ω 

f 
Hz 
Working frequency.
f>0 ⇒ fixed frequency
f=0 ⇒ external control of frequency, may be variable 
min 
V 
Minimum detectable amplitude of the signal 


DeadTime 
Dead time control 
IN 
Input, floating 
OUT 
Output, 1 Ω 

Vhigh
Vlow 
V 
Output logic levels, default <1,0> 
td 
s 
The delay time 
ref 
V 
Input logic level threshold 
Hidden: 
td 
s 
Gate delay time, LTspice specific for Adevices, default null 


DeadZone 
Dead zone 
IN 
Input, floating 
OUT 
Output, 1 Ω 

dz=<0..∞> 
V 
Sets the deadzone 


Delay 
Analog, e^{st} , or digital, z^{t} , time delay (it's made with a tline ) 
IN 
Input, floating 
OUT 
Output, 1 Ω 



Diff 
Differentiator (current source with a parallel inductor) 
IN 
Input, floating 
OUT 
Output, 1/ω_{c}Ω 

tau 
s 
The timeconstant 
Hidden: 
Rser Rpar 
Ω 
Inductor's series and parallel resistances, default 0 Ω, respectively 1 GΩ 


FFT 
It's actually a CFT block 
IN 
Input, floating 
A[0:31] 
Bus output, sine amplitudes (including DC, a[0] ), 1 Ω 
B[1:31] 
Bus output, cosine amplitudes, 1 Ω 
SIN[1:31] 
Bus output, sine harmonics, 1 Ω 
COS[1:31] 
Bus output, cosine harmonics, 1 Ω 

f 
Hz 
The working frequency 
N=<0..31> 

The number of harmonics 


Filter 
The universal filter for LTspice discussed at large in Filter Manual (top menu) 



FreqDet 
Frequency meter/detector 
IN 
Input, floating 
OUT 
Output, 1 Ω 

limit 
s 
The minimum detectable period. E.g. for max 1kHz ⇒ limit=1m 
Hidden: 
tripdt 
s 
LTspice specific for Bsources. Internally, tripdv=tripdt/2 


Gain 
Linear/dB gain/buffer 
IN 
Input, floating 
OUT 
Output 

G=<∞..∞> 

Sets the gain 
dB=<0,1> 

dB=0 ⇒ linear gain
dB=1 ⇒ gain in dB 
Rout 
Ω 
Output resistance 


Integ_r 
Resettable integrator with internal/external period 
IN 
Input, floating 
OUT 
Output, 1 Ω 
RESET 
External reset input, valid for V(RESET)>0 , 1 GΩ 
TAU 
External period input, 1 GΩ 

tau 
s 
The period of integration
tau>0 ⇒ fixed period
tau=0 ⇒ external period at pin TAU 


LeadLag
LeadLag2 
Voltage controlled lead/lag. There are two versions: LeadLag is made with a passive LC approach, LeadLag2 is made with sin/cos multiplication.
1. The first one should perform faster than the second for large amplitudes of the input signal; instead, the output needs a few periods of settling time for any change in phase (even for the beginning of the simulation).
2. For the second, the quadrature input is realized with a ddt() , so the response is stable right from the beginning; instead, any steep transients at the input will be differentiated and present at the output. The same is valid for .uic 
IN 
Input, floating 
OUT 
Output, 1 Ω 
PHI 
External phase control input, valid for phi=0 , 1 GΩ 

f 
Hz 
The working frequency 
phi 
rad 
The phase displacement. Its value is wrapped internally. 
Hidden: 
q 
rad 
For LeadLag only. When phi gets close to π/2 , there may be numerical problems, so this tweak makes phi=π/2+q . Default is 1µ. 


Lim 
Hardlimitter. It doesn't use if() or limit() or any behavioural source; it's a Gsource with a table() 
IN 
Input, floating 
OUT 
Output, 1 Ω 

Min Max 
V 
The lower and upper limits 


MUX 
Simple analog multiplexer. When int[V(CTL)]=1 , output follows input #1, when int[V(CTL)]=2 output follows input #2, and so on 
<1:8> 
Inputs, floating 
OUT 
Output, 1 Ω 
CTL 
External input select voltage, floating 



PhaseDet 
Fixed frequency phase detector/meter, it has a one period lag 
IN 
Input, floating 
OUT 
Output, 1 Ω 

f 
Hz 
The working frequency 
deg=<0,1> 

0 means [rad ], 1 means [deg ] 
Hidden: 
Rpar 
Ω 
Dummy parallel resistance for the integrator's capacitor, default 1 GΩ 


PID 
Proportionalintegralderivative control (parallel). Any combination works: PID, PI, PD, ID, P, I, D, none. There is also a (parallel) digital version, PIDd , which can be chosen by either renaming the device's name or by selecting the PIDd from the SpiceModel line (in the symbol's properties) 
<1:8> 
Inputs, floating 
OUT 
Output, 1 Ω 
CTL 
External input select voltage, floating 

Kp 

The proportional gain 
Ki 

The integral gain 
Kd 

The derivative gain 
Ts 
s 
The sampling time (PIDd only) 


PLL 
Phaselocked loop. It accepts both single and/or quadratureinput and outputs unity sin/cos, frequency and the angle. If used as a singleinput, the IN input must be used 
IN 
Normal input, floating 
INQ 
Quadrature input, 1 GΩ 
SIN 
Unity sine ouput, 1 Ω 
COS 
Unity cosine output, 1 Ω 
FREQ 
Frequency output, it obeys internal parameters Kd and K0 . Its output impedance is
tau2/tau1+1/(ω⋅tau1) 
THETA 
Angle, <0..2π> , 1 Ω 

f 
Hz 
The central frequency 
tau1
tau2 
s 
The time constants for the PI loop 
fc=<0,1> 

0 disables, 1 enables the internal lowpass filter, done with an adjustable movingaverage over one period 
Kd 

The phasedetector multiplier 
K0 

VCO gain 


SampledSource 
LTspice's SINE and PULSE sources, sampled. Only one of them can be active at a time. The parameters are the same as LTspice's, with some exceptions and additions 
1 
Or the + pin 
2 
Or the  pin 
CLK 
I/O for the sample clock. If external clock is used, it's better to set f0, tr, td to zero to not slow down the simulation (i.e. the source is not disabled). 1 GΩ 

f0 
Hz 
The sampling frequency 
SP=<0,1> 

0 ⇒ SINE source
1 ⇒ PULSE source 
td 
s 
Delay time of the clock pulse (rising edge) 
tr 
s 
Rising edge of the clock pulse 
Rout=<0..∞> 
Ω 
Rout=0 ⇒ voltage source
Rout>0 ⇒ current source 
Voffset
Vamp
Freq
Tdelay
Theta
Phi
Ncycles 

The parameters for the SINE source. Tdelay replaces Td 
V1
V2
Tdelay
Trise
Tfall
Ton
1/Freq
Ncycles 

The parameters for the PULSE source. 1/Freq replaces Period 
ac
acphase 

The AC amplitude and phase, common to both 
Hidden: 
vhigh
vlow 
V 
The SAMPLEHOLD 's upper and lower levels 
tripdt 
s 
LTspice specific for Adevices (the SAMPLEHOLD ) 


StateSpace 
1st, 2nd and 3rd order SISO statespace block. The parameters use two indices that mark the matrix elements. Not all parameters are used, see the note 
IN 
Input, floating 
OUT 
Output, 1 Ω 

A11 A12 A13
A21 A22 A23
A31 A32 A33 

The A matrix 
B11
B21
B31 

The B matrix 
C11 C12 C13 

The C matrix 
D11 

The D parameter 
ic1
ic2
ic3 

The three initial conditions 


UpDnSpl 
Up/downsampler, with or without external sync, .AC friendly 
1 
Input, floating 
2 
Output, 1 Ω 
3 
I/O clock. External sync must match the output's sampling frequency. 

f0 
Hz 
The sampling frequency, it must be set to match the input's 
N=<∞..∞> 

N>0 ⇒ upsampler
N<0 ⇒ downsampler 
SH=<0,1> 

SH=0 ⇒ usually set for .AC analysis, disables up/downsampling (input follower)
SH=1 ⇒ usually set for .TRAN analysis, enables up/downsampling 
Hidden: 
td 
s 
Delay time for the clock, default null 
tr 
s 
Rise time for the clock, default 1m/f0 
lim 
V 
The upper and lower limits for the SAMPLEHOLD (downsampler), defaults Vhigh=lim, Vlow=lim 
ref 
V 
Reference voltage for the SAMPELHOLD 's clock (downsampler), default 0.5 

